The present invention relates to an information processing device in an electronic computer, capable of processing instructions including branch instructions.
Pipe-line control systems have been known in the art, which process branch instructions at very high speeds.
In these systems, a minimum of four cycles are required for the processing, beginning with the decoding of the presence of a branch instruction until the decoding of a branch target instruction, which is stored at a branch target address in the branch instruction.
If a cache memory is provided and the branch target instruction is present in the cache memory, the instruction processing would require several cycles, such as the cycle for providing an effective branch target address, the cycle for referencing a cache index memory, the cycle for reading the branch target instruction at the branch target address from the cache memory, and the cycle for decoding the read instruction.
If the branch target instruction at the corresponding branch target address is not present in the cache memory or the cache memory itself is not provided, a larger number of cycles is needed. In the prior art, therefore, a considerable amount of time has been necessary for instruction processing, which has hampered an electronic computer from operating at a greater processing efficiency.
Generally, in the pipe-line control system, information processing is carried out through a prediction as to whether the branch is established or not. If the prediction is wrong, the processing in progress is cancelled and an additional number of cycles becomes necessary.